1. Field of the Invention
The invention relates generally to a boosting circuit, and more particularly to, a boosting circuit capable of reducing a read access time upon a data read operation in a memory cell of a semiconductor device, minimizing loss of current and generating a stabilized word line voltage.
2. Description of the Prior Art
In a memory cell of EEPROM (electrically erasable and programmable read only memory) being a kind of a nonvolatile semiconductor memory device, a program operation is performed in which electrons are accumulated at a floating gate electrode. A read operation is performed in which variation in the threshold voltage (Vth) depending on whether the electrons exist or not is detected. The EEPROM includes a flash EEPROM (hereinafter called xe2x80x98flash memory devicexe2x80x99) in which data is erased in the entire memory cell array or data is erased in a block unit by dividing the memory cell array in given blocks.
Generally, the memory cells of the flash memory cell are classified into a stack gate type and a split gate type, depending on its structure. For example, as shown in FIG. 8, the memory cell of the stack gate type includes a source region 804 and a drain region 806 that are formed in a semiconductor substrate 802, and a gate oxide film 808, a floating gate 810, a dielectric film 812 and a control gate 814 that are sequentially formed on the semiconductor substrate 802.
The program operation of the memory cell of the stack gate type is performed by applying a ground voltage (0V), a source voltage (Vs) and a bulk voltage (Vb) to the source region 804 and the semiconductor substrate 802 (i.e., bulk), respectively, a gate voltage (Vg) of a positive high voltage (program voltage) (for example, +9V through +10V) to the control gate 814, and a drain voltage (Vd) (for example, +5V through +6V) to the drain region 806, in order to generate hot carriers, as shown in Table 1 below and FIG. 9. The hot carriers are generated since electrons in the bulk are accumulated at the floating gate 810 by an electric field of the gate voltage (Vg) applied to the control gate 814 and electric charges supplied to the drain region 806 are accumulated. After the program operation is finished, the memory cells have a program threshold voltage of a target program voltage range (for example, 6V through 7V).
The erase operation of the memory cell of the stack gate type is performed by applying a negative high voltage (erase voltage) (for example, xe2x88x929V through xe2x88x9210V) to the control gate 814 and the bulk voltage (Vb) (for example, +5V through +6V) to the bulk, in order to cause a F-N (Fowler-Nordheim) tunneling phenomenon, as shown in Table 1 below. The memory cells are erased in a sector unit sharing the bulk region. The F-N tunneling phenomenon serves to discharge the electrons accumulated at the floating gate 808 to the source region 804, so that the memory cells have an erase threshold voltage of a given voltage range (for example, 1V through 3V).
In the memory cells threshold voltages of which are increased through the program operation, injection of current into the source region 804 from the drain region 806 is prevented upon the read operation, so that the memory cells are in an off state. Also, in the memory cells the threshold voltage of which is lowered through the erase operation, current is injected from the drain region 806 to the source region 804, so that they are in an on state.
In the structure of the flash memory array, the flash memory cells are constructed to share the bulk region for high-integration. Therefore, the flash memory cells included in a single sector are simultaneously erased. At this time, if all the flash memory cells are erased at the same time, some flash memory cells (hereinafter, called xe2x80x98over-erased memory cellsxe2x80x99) having the threshold voltage of below 0V, of the flash memory cells, exist due to uniformity of the threshold voltage held by the respective flash memory cells. In order to compensate for this, an over-erase repair operation for distributing the threshold voltage of the over-erased flash memory cells within the erase threshold voltage range is performed. As in Table 1 below, the over-erase repair operation is performed by applying the gate voltage (Vg) (for example, +3V) to the control gate 814 and the drain voltage (Vd) (for example, +5 through +6V) to the drain region 806, and also grounding the source region 804 and the bulk.
As described above, in order for the program operation, erase operation and read operation of the flash memory device to be performed, a function of the high voltage generating circuit for generating high voltages (for example, Vpgm (program voltage), Vera (erase voltage) and Vrea (read voltage)) supplied to the control gate of the memory cell is very important.
Recently, as there is a trend that all the semiconductor memory devices have a low voltage, the operation of the flash memory device under an ultra low voltage (for example, below 2V or below 1.7V) is required. In line with this trend, in order to maintain a rapid operation speed of, the flash memory device, a function of the high voltage generating circuit is very important.
The read voltage generating circuit for performing the read operation in the high voltage generating circuit includes the bootstrapping circuit in order to increase the read operation speed. The bootstrapping trap circuit uses a low-potential power supply voltage to boost it and then supplies the boosted voltage to the word lines via a row decoder. In case that the low-potential power supply voltage is boosted using the bootstrapping circuit, if the voltage of the word line boosted by the bootstrapping circuit is too low, it is difficult to exactly read current of the memory cell. On the contrary, if the voltage of the word line is too high, there occurs a problem in data retention since stress is applied to the control gate of the memory cell.
In the above, in order to solve the latter case, a clamp circuit for dropping the voltage that is too high boosted by the bootstrapping circuit (hereinafter, called xe2x80x98the boosting voltagexe2x80x99) to a target voltage, is posited at the rear of the bootstrapping circuit. This will be below described by reference to FIG. 10.
FIG. 10 is a block diagram of the boosting circuit of a common flash memory device. Meanwhile, xe2x80x98VDIVxe2x80x99 among the signals in FIG. 12 below is a divided voltage that is generated in a clamp circuit 1030 and is compared with the reference voltage (Vref). Also, xe2x80x98W/Lxe2x80x99 is a voltage that is applied to a word line.
Referring now to FIG. 10, the boosting circuit 1000 includes a bootstrapping circuit 1010, a reference voltage generator 1020 and a clamp circuit 1030. The bootstrapping circuit 1010 boosts the low-potential power supply voltage (Low Vcc; LVcc) (for example, 2.5V) or the high-potential power supply voltage (High Vcc; HVcc) (for example, 3.8V) to output the boosted voltage. The reference voltage generator 1020 is constructed depending on the enable bar signal (Enb) being a synchronization signal to output the reference voltage (Vref). Also, the clamp circuit 1030 is driven by an enable signal (EN) and an enable bar signal (ENb) to compare the boosting voltage (VBOOT) from the bootstrapping circuit 1010 and the reference voltage (Vref). If the boosting voltage (VBOOT) is higher than the reference voltage (Vref), the clamp circuit 1030 drops the boosting voltage (VBOOT) to a target voltage to output a word line voltage.
Meanwhile, the enable signal (EN) and the enable bar signal (ENb) could be obtained thorough an enable signal generating circuit 1100 shown in FIG. 11. The enable signal generating circuit 1100 includes a NOR gate (NOR) for negatively logically combining the clamp enable signal (clamp_en) to drive the clamp circuit 1030 and the clamp signal (clamp) being an output signal of the clamp circuit 1030, an inverter (INV1) for inverting an output signal of the NOR gate (NOR), and an inverter (INV2) for inverting the output signal the inverter (INV1) (i.e., the enable signal (EN)) to output the enable bar signal (ENb).
However, this boosting circuit 1000 uses the clamp circuit 1030 in order to generate the word line voltage. Therefore, as shown in FIG. 12, a stable word line voltage could not be generated. Further, in order to generate the stable word line voltage, an access time (that is, time consumed to drop the boosting voltage to the target voltage) is delayed. In addition, if a rapid access time is considered in an effort to solve this problem, many problems are occurred in stabilizing the semiconductor device since the word line voltage is under shoot (see xe2x80x98Axe2x80x99 in FIG. 12). Also, there is a problem that read active current could not be controlled in the low-potential power supply voltage (LVcc) region that is not sensed in a clamping period.
The present invention is contrived to solve the above problems and an object of the present invention is to generate rapid and stabilized word line voltage upon a data read operation.
In order to accomplish the above object, a boosting circuit according to the present invention, is characterized in that it comprises a booth trap circuit for boosting a first voltage to output a second voltage, a pre-select clamp circuit selectively driven by a bias voltage to drop the second voltage to a given voltage level, wherein the amount of the bias voltage is determined by the amount of the first voltage, and a clamp circuit for dropping the second voltage that is dropped by the pre-select clamp circuit to a target voltage.